This invention relates generally to computer systems, and more particularly to the transfer of data between a data transfer device an asynchronous portion of a computer system.
As it is known in the art, computer systems generally include at least one central processing unit (CPU), a main memory for storing data, at least one input/output (I/O) device, and a system bus coupling the aforementioned devices to the CPU. The I/O device generally has a port which is coupled to an I/O bus which provides for access to one or more peripherals.
Generally, I/O devices are used to transfer data between the system bus and the I/O bus such that peripherals resident on the I/O bus are coupled to the remainder of the computer system. Many different types of peripherals, such as mass storage devices, i.e., disk drives, tape drives, etc., printers, other computer systems, and other I/O busses, etc., may be resident on the I/O bus. These peripherals generally have many different characteristics, including the speed at which they operate. Often, to take advantage of the operating speed of the fastest devices while still allowing slower devices to operate on the I/O bus, the I/O bus is provided as an asynchronous bus. An asynchronous bus is one in which there is no common clock or timing signal from which other signals, such as address, data, and control signals, are related. A synchronous bus is one is which all devices on the bus assert and deassert bus signals relative to transitions, i.e., assertions and/or deassertions, of a common clock or timing signal.
Asynchronous busses generally operate via handshake signals sent between devices on the bus. Each handshake signal is usually associated with one or more bus signals, and if one device causes a transition of a handshake signal, for example, an address strobe handshake signal, this usually indicates that its associated signals, i.e., the address signals, are valid. All appropriate devices on the bus will assert a corresponding handshake signal to indicate that they received the signals, i.e., address signals. In this manner, a fast device can communicate with a slow device by waiting for the slow device's related handshake signals which allows each device to operate as fast as possible.
Generally, it is necessary in a computer system such as the one described above, to transfer data to and from the asynchronous I/O bus. Prior techniques use a bus interface circuit to control transfers with the asynchronous bus. One technique synchronizes the asynchronous bus handshake signals prior to using them. A problem with this approach is that it limits the speed of the data transfer rate. An alternative approach is to use an asynchronous interface to transfer data with the asynchronous bus. An advantage of this approach is that data transfer on the asynchronous bus is very fast. A disadvantage is that the asynchronous interface is generally very complicated and expensive.
As is also known, a bus transaction, whether synchronous or asynchronous, generally involves a command/address phase or cycle, which may be an initial transfer of information related to the transaction being initiated, followed by a data phase or cycle, which may be many transfers of data. A device performs a transaction on the bus by first gaining access to the bus through some form of bus arbitration. After gaining access, the device begins the transaction by sending a command and an address on the bus (command/address phase). All devices on the bus examine the address and command. The devices often check for parity and other errors. The devices also decode the address to determine if they are a target, hereinafter referred to as a bus slave device, of the transaction. The bus slave device or devices must further decode the command and address information to determine the appropriate logical path to follow. Busses, particularly I/O busses where many different types of peripherals having different characteristics may reside, are very complicated. There may be several ways for a device to proceed after decoding the address and command information.
Whether the bus is a synchronous or asynchronous bus, transaction control of the bus is often provided by state machines, i.e., sequential circuits. One type of state machine is a synchronous state machine which uses storage elements called flip-flops that are allowed to change their binary value only at discrete instants of time. Synchronous state machines generally include combinatorial logic circuits which implement so called "state equations". The state equations define the operation or flow of the state machine. In response to the outputs from the combinatorial logic circuits, the flip-flops generate output bits termed state bits which define the states of the state machine. The combinatorial logic receives inputs from external logic and the flip-flops, and provides outputs to external logic and to the flip-flops. The transition of a clock signal allows the flip-flops to operate on their input signals to produce the next output states of the flip-flops. The cycle time, i.e., assertion edge to assertion edge, of the clock signal may be chosen to be the smallest value which will allow the flip-flops to operate on their input signals and allow the combinatorial logic to operate on the changed inputs from the flip-flops. Therefore, the clock signal may not transition until the flip-flop inputs are valid, i.e. settled from transition, "glitch-free", or "noise-free", and have been valid for at least a time equal to the input set up time of the flip-flops. While this requirement prevents the synchronous state machine from changing state prematurely or incorrectly due to glitches, it also limits the speed of the state machine to the clock cycle which is limited to the propagation delay through the slowest path.
An I/O device which utilizes a synchronous state machine to transfer data with an asynchronous bus must also synchronize all the received asynchronous bus handshake signals prior to using them. To synchronize asynchronous signals, a two stage flip-flop apparatus may be used, i.e., a dual stage synchronizer. With a dual stage synchronizer, the asynchronous signal is fed to a first flip-flop input and the synchronizing clock is used to allow the signal value to pass through the flip-flop appearing at an output of the first flip-flop if the signal reaches the flip-flop prior to the clock transition. The output from the first flip-flop is then fed into an input of a second flip-flop which is controlled in a similar fashion by the clock signal. The two stages are necessary to prevent metastability, i.e., if the asynchronous signal transitions at or just before the clock transition, the output from the first flip-flop may not be stable. The second flip-flop allows an entire clock cycle for the first flip-flop's output to stabilize before passing the value of the signal to its output. The synchronous state machine may then operate on the output of the second flip-flop on a next clock transition. Worse case, the asynchronous signal will transition just after the clock transition, and the first flip-flop will not pass the value on until the following clock transition. If this happens, then the synchronous state machine will not operate on the signal until a fourth clock transition. Accordingly, a problem with using a synchronous state machine to interface to an asynchronous bus is that it requires circuitry to synchronize the received asynchronous handshake signals. This circuitry or "synchronizer" introduces a high latency period between data being ready to transfer and data being transferred since the synchronizer invariably delays transitions of the asynchronous signals by up to three to four clock cycles.
Another type of state machine is the asynchronous state machine. Asynchronous state machines are basically combinatorial circuits with feedback paths whose outputs depend upon the order in which its input variables change. Similar to the synchronous state machine, the combinatorial logic implements state equations which define the operation/flow of the state machine. However, there are no storage elements, i.e., flip-flops, and, therefore, the outputs of the asynchronous state machine may be affected at any instant of time by changes in any inputs to the state machine. The combinatorial logic which comprises the asynchronous state machine generates the state bits and other output signals, and, therefore, changes from one state to the next are not controlled by a clock signal like the synchronous state machine. Thus, the asynchronous state machine changes states as fast as the combinatorial logic can operate on the received signals. In general, an asynchronous state machine interface to an asynchronous bus is much faster than the aforementioned synchronous state machine. To prevent glitches on state bits from forcing the asynchronous state machine into invalid states, only one state bit is permitted to change each time the state machine changes state. Therefore, only that state bit has the possibility of glitching and, thus, the asynchronous state machine will not transition to an incorrect state. In general, this leads to a large number of required states and, therefore, to a large number of state bits which increase the amount of circuitry necessary to implement the state machine.
Asynchronous state machines must also be designed to be hazard proof. A hazard may occur where inputs to the state machine are changing, and, thus, the state of the state machine is changing, but some outputs of the state machine are suppose to remain steady. In this case, as the state is changing, an output may momentarily change (i.e., glitch) to a different level than the steady value which may cause the state machine to improperly move to an incorrect state. To overcome this problem, the asynchronous state machine equations are provided with added terms, i.e., hazard terms, to prevent these possible glitches from causing transitions to wrong states. These added hazard terms further increase the amount of circuitry required to implement the asynchronous state machine.
Accordingly, use of asynchronous interfaces to interface to an asynchronous bus is the preferred approach if speed is a primary objective. However, as computer systems become more complex, bus structures associated with these systems become more complex. One problem with using an asynchronous interface to interface to such a complex bus, therefore, is that the interface becomes correspondingly complex, and as the complexity of the bus structure increases, the size and cost of the interface increases concomitant therewith.
In addition to the situation mentioned above, there are many other situations in which data must be transferred with an asynchronous bus. The above mentioned system bus may be synchronous or asynchronous. If the system bus is asynchronous, the difficulties involved with interfacing to an asynchronous bus occur when interfacing to the system bus.